In integrated circuits, there is normally a need to reduce electromagnetic interference emissions. Steep signal edges lead to relatively large emitted and conducted emissions, especially during operation with high-frequency, digital signals. However, to ensure that electronic systems do not significantly impede the operation of other electronic system, regulatory measures have been imposed, such as the establishment of severity values, which are intended to guarantee the electromagnetic compatibility (EMC) of different systems. Electromagnetic compatibility (EMC) relates to both allowable electromagnetic emissions and required resistance to interference.
One method of reducing high-frequency signal components within the frequency spectrum of a digital signal includes reducing the slopes of rising and falling edges of the digital signals. Therefore, efforts have been made to reduce the slopes of both rising and falling signal edges of digital signals so as to comply with EMC standards or EMC specifications, and to guarantee reliable operation of the circuits.
In the rapid digital signal processing used today, such as in digital signal processors, digital signals are designed to be as fast as possible, often in the range of a hundred picoseconds. This leads to the large, high-frequency spectral component of the signals. In addition, integrated circuits used in fast digital signal processing normally occupy a small amount of surface area on a chip and consume low power during operation.
In U.S. Pat. No. 6,225,844, an output stage is disclosed, which can be operated stably with a relatively small signal slope. The specified output stage comprises two CMOS inverter stages connected in parallel, with respect to their load paths, between a reference potential connection and a supply potential connection. An output signal with reduced edge slope can be obtained from these inverter stages. Whereas the first of the two input stages is directly driven by the input signal, an additional control circuit for influencing signal edge slope is provided to drive the gate electrodes of the transistors of the second transistor inverter stage. This circuit enables the two transistors of the second output stage to be switched on or off in a controlled manner. Because threshold values of the transistors are used to drive the second output stage, the principle described above can only be used to construct a two-stage circuit array.
A circuit array for reducing the edge slope of an output signal is also described in U.S. Pat. No. 5,140,194. In this case, several CMOS inverter output stages are connected in parallel. Delay times are generated to drive the various inverter stages. According to the patent, the delay times are generated with RC time constants. A disadvantage of this approach, however, is that it involves use of resistors having narrow tolerance ranges and that require a relatively large chip surface area. Alternatively, it is also proposed that the RC elements be replaced with delay elements, which are also difficult to implement. The disadvantage remains of having to adjust the time constant individually for each inverter stage on the output end, and of having to implement individually in terms of circuit technology.
Another disadvantage shared by the above-described circuit arrays is that the slope of the output signal is dependent on the characteristics of the input signal.